The present invention generally relates to semiconductor memory devices, and more particularly to a synchronous semiconductor memory device such as a synchronous random access memory having latch circuits for receiving a write data and a write command.
FIG. 1 shows an example of a conventional asynchronous random access memory (RAM). The RAM generally has a write command input buffer circuit 1 for receiving an external write command (write enable signal) WE, a write data input buffer circuit 2 for receiving a write data DIN, a write control circuit 3, a level shift circuit 4, and a memory cell array 5 having a plurality of memory cells MC. GND and V.sub.EE denote power source voltages, and VR1 and VR2 denote reference voltages. The write control circuit 3 supplies the write data DIN to the memory cell array 5 in a write mode. In a read mode, the write control circuit 3 cuts off the supply of the write data DIN and applies a constant read potential to the memory cell array 5. The write and read modes are controlled by the write command WE, and the write mode is selected by a low-level write command WE and the read mode is selected by a high-level write command WE. An output signal of the input buffer circuit 1 which receives the write command WE is applied to transistors Q.sub.32 and Q.sub.34 of the write control circuit 3.
A transistor Qa for cancelling a noise is connected to the input buffer circuits 1 and 2 as indicated by a phantom line in FIG. 1. During a time other than a write process, a change in the write data DIN becomes a source of the noise and the noise would be transmitted to the write control circuit 3 if the transistor Qa were not provided. In this case, the noise would destroy an information content of the memory cell MC through the write control circuit 3. Hence, the transistor Qa has a function of clamping a potential of a write process signal so as to prevent the noise from destroying the information content of the memory cell MC.
FIGS. 2(A) through 2(F) are time charts for explaining the operation of the conventional asynchronous RAM with and without the transistor Qa for cancelling the noise. FIGS. 2(A) and 2(B) respectively show the write data DIN and the write command WE. FIGS. 2(C) and 2(D) respectively show write process signals Sa1 and Sb1 at nodes A1 and B1 in FIG. 1 then the transistor Qa is not provided, while FIGS. 2(E) and 2(F) respectively show write process signals Sa2 and Sb2 at the nodes A1 and B1 when the transistor Qa is provided. In FIGS. 2(C) and 2(D), N1 denotes a source of the noise introduced in the write process signals Sa1 and Sb1 due to a change in the write data DIN.
The node Al is connected to a base of a transistor Q.sub.33 of the write control circuit 3 to which the write process signal Sa1 or Sa2 is supplied. The node B1 is connected to a base of a transistor Q.sub.31 of the write control circuit 3 to which the write process signal Sb1 or Sb2 is supplied.
When the transistor Qa is not provided in FIG. 1, the write process signals Sa1 and Sb1 outputted from the input buffer 2 and supplied to the write control circuit 3 through the respective nodes A1 and B1 change when the write data DIN changes, regardless of whether the RAM is in the write mode or the read mode. For this reason, the change in the write data DIN in the read mode causes a change in the write process signals Sa1 and Sb1 at the respective nodes A1 and B1 and becomes a source of a noise with respect to the write control circuit 3. On the other hand, in the read mode, the write control circuit 3 applies a constant read potential to the memory cell array 5. Thus, the noise source N1 shown in FIGS. 2(C) and 2(D) varies the read potential in the read mode and makes undesirable effects on the memory cells MC of the memory cell array 5.
In other words, the noise in the read potential becomes a noise in a detecting potential for detecting the information content of the memory cell MC on a bit line BL which is coupled to the ground through a transistor Tr. Accordingly, the noise deteriorates the access time of the RAM and in an extreme case the information content of the memory cell MC is inverted thereby causing an erroneous write operation.
In order to eliminate the above described problems, the conventional asynchronous RAM uses the transistor Qa to clamp the change in the write data DIN at an input stage of the input buffer 2. A base of the transistor Qa is controlled by the write command WE from the input buffer 1. In the read mode, the transistor Qa substantially fixes the write data DIN to a high level responsive to a high-level write command WE. In this case, the potential change in the write process signals Sa2 and Sb2 respectively shown in FIGS. 2(E) and 2(F) only occurs during a low-level period of the write command WE in the write cycle, that is, only in the write mode, and the potentials of the write process signals Sa2 and Sb2 are otherwise fixed regardless of the change in the write data DIN. Therefore, it is possible to completely eliminate the source of the noise with respect to the write control circuit 3 caused by the change in the write data DIN.
On the other hand, there is a conceivable synchronous RAM shown in FIG. 3 which has latch circuits and controls the external write command WE and the write data DIN responsive to a clock signal CLK. But even when the transistor Qa is connected to the synchronous RAM shown in FIG. 3, it is impossible to eliminate the problem of the noise caused by the change in the write data DIN.
In FIG. 3, the synchronous RAM generally has a write command input latch circuit 6 for receiving the write command WE, a write data input latch circuit 7 for receiving the write data DIN, a write control circuit 8, a write pulse generating circuit 9 for generating an internal write pulse signal, and a clock gate circuit 10 for outputting to the write pulse generating circuit 9 a start signal for starting the generation of the internal write pulse signal based on a clock signal CLK and the write command WE. GND and V.sub.EE denote power source voltages, and VR1, VR2 and VR3 denote reference voltages. The write control circuit 8 supplies the write data DIN to the memory cell array (not shown) in the write mode. On the other hand, in the read mode, the write control circuit 8 cuts off the supply of the write data DIN and applies a constant read potential to the memory cell array. The transistor Qa is connected as indicated by a phantom line in FIG. 3.
FIGS. 4(A) through 4(H) are time charts for explaining the operation of the conceivable synchronous RAM with and without the transistor Qa for cancelling the noise. FIGS. 4(A), 4(B), 4(C) and 4(D) respectively show the clock signal CLK, the write data DIN, the write command WE and a signal SC1 at a node C1. t.sub.S denotes a set up time and t.sub.H denotes a hold time of the latch circuit 6. The signal SC1 at the node C1 is the internal write pulse signal outputted from the write pulse generating circuit 9. This internal write pulse signal SC1 is applied to bases of transistors Q.sub.82 and Q.sub.84 of the write control circuit 8.
FIGS. 4(E) and 4(F) respectively show write process signals Sa3 and Sb3 at nodes A2 and B2 in FIG. 3 when the write command WE has a waveform indicated by .circle.1 in FIG. 4(C), while FIGS. 4(G) and 4(H) respectively show write process signals Sa4 and Sb4 at the nodes A2 and B2 when the write command WE has a waveform indicated by .circle.2 in FIG. 4(C). In FIGS. 4(G) and 4(H), N2 and N3 respectively denote a source of the noise introduced in the write process signals Sa4 and Sb4 due to a change in the write data DIN. The write process signals Sa3, Sb3, Sa4 and Sb4 are internal write data signals formed depending on the write data DIN applied to the input latch circuit 7. The node A2 is connected to a base of a transistor Q.sub.83 of the write control circuit 8, and the write process signal Sa3 or Sa4 is applied to the base of the transistor Q.sub.83. The node B2 is connected to a base of a transistor Q.sub.81 of the write control circuit 8, and the write process signal Sb3 or Sb4 is applied to the base of the transistor Q.sub.81.
Next, a description will be given on why the noise cannot be eliminated in the conceivable synchronous RAM even when the transistor Qa is provided as shown in FIG. 3.
In FIG. 4(C), the setting with respect to the write command WE of the synchronous RAM is made so that the write command WE is "true" only during a time [t.sub.S (min)+t.sub.H (min)] because the latch circuit 6 has the data store function, where t.sub.H (min) is the minimum hold time and t.sub.S (min) is the minimum set up time with respect to the rising edge of the clock signal CLK. In other words, the write or read mode within one cycle of the clock signal CLK is determined by the high or low level state of the write command WE at the rising edge of the clock signal CLK. Accordingly, the condition on the write command WE is that the write command WE is fixed to the high or low level at least during the time t.sub.S (min) before the rising edge of the clock signal CLK and the time t.sub.H (min) after the rising edge of the clock signal CLK. Thus, the write command WE may change during a time other than the time [t.sub.S (min)+t.sub.H (min)] and such a chage will not be an effective signal against the write or read operation.
Therefore, in a first case, the write command WE becomes low immediately before the write cycle (that is, the minimum set up time t.sub.S (min) before the rising edge of the clock signal CLK) and ends the minimum hold time t.sub.H (min) after the rising edge of the clock signal CLK as indicated by the solid line .circle.1 in FIG. 4(C). On the other hand, in a second case, the write command WE remains low even after the minimum hold time t.sub.H (min) elapses from the rising edge of the clock signal CLK as indicated by the broken line .circle.2 in FIG. 4(C) or the write command WE becomes low immediately after the minimum hold time t.sub.H (min) in the read cycle.
The internal write pulse signal SC1 is formed by the write pulse generating circuit 9 which is triggered by the low-level write command WE entered at the rising edge of the clock signal CLK. This internal write pulse signal SC1 is applied to the bases of transistors Q.sub.82 and Q.sub.84 of the write control circuit 8 as described before.
The input latch circuits 6 and 7 are provided to enter the write data DIN at the rising edge of the clock signal CLK, and the write data DIN is latched during the high-level period of the clock signal CLK while the write data DIN is passed as it is during the low-level period of the clock signal CLK.
In the first and second cases described above, the write data DIN is entered in the write mode responsive to the low-level write command WE. However, when the transistor Qa carries out a clamp operation responsive to the high-level write command WE, the potentials at the nodes A2 and B2 become fixed through mutually different courses between the first and second cases. In the synchronous RAM, the external write command WE need only become high or low for a predetermined time before and after the rising edge of the clock signal CLK, and the write command WE may otherwise change and become low when the write data DIN changes or become low in the read cycle, for example. As a result, the more use of the transistor Qa to carry out a clamping operation responsive to the write command WE cannot eliminate the source of the noise, and the clamping cannot be carried out in the read mode.
In other words, in the first case, a preparation takes place for the clamping operation of the transistor Qa when the write command WE changes to the high level immediately after the minimum hold time t.sub.H (min) of the input latch circuit 6, and the latch circuit 7 enters the clamping potential at the falling edge of the clock signal CLK which occurs thereafter. As a result, the write process signals Sa3 and Sb3 at the respective nodes A2 and B2 become fixed potentials. Because the write command WE remains at the high level even in the read cycle, the change in the write data DIN is not transmitted to the nodes A2 and B2 inside the RAM. Hence, in the first case where the write command WE becomes low only in the write mode as in the case of the conventional asynchronous RAM described before in conjunction with FIGS. 1 and 2(A) through 2(F), it is possible to eliminate the source of the noise by use of the transistor Qa.
But in the second case, the driving of the transistor Qa initiated by the change of the write command WE to the high level from the low level is only carried out immediately (that is, the minimum set up time t.sub.S (min)) before the rising edge of the clock signal CLK in the read cycle. For this reason, when the write command WE changes in a state where the clock signal CLK is low (that is, the input latch circuit 7 passes the write data DIN as it is) and the write command WE is low (that is, no clamping operation is carried out), the noise source N2 is transmitted to the nodes A2 and B2 thereby changing the potentials of the write process signals Sa4 and Sb4. Furthermore, since the write command WE becomes low and the clock signal CLK becomes low at the latter half of the read cycle, the next change in the write data DIN is transmitted to the inside of the RAM as a noise source N3.
Accordingly, although it is possible to eliminate the noise by use of the transistor Qa in the p first case, the transistor Qa is ineffective in the second case where the write command WE also becomes low during a time other than the predetermined time described above. Hence, in the second case, the change in the write data DIN is transmitted to the memory cell array as the noise source N2 or N3, and there are problems in that the memory cell may become destroyed or an erroneous write operation may be carried out.